The invention relates to semiconductor memories and specifically to electrically programmable non-volatile memories, currently called EPROM; in particular, the invention relates to the manufacturing of floating gate memories.
For obtaining large-scale memories, for example memories able to store up to 16 megabits, the size of each cell of the memory has to be reduced as much as possible.
But of course, there is a limitation due to physical problems and in particular to the size of photolithographic patterns; another limitation is due to parasitic electrical parameters associated to the manufacturing process which disturb the memory operation.
An elementary memory point of a conventional memory is shown on FIGS. 1A and 1B, FIG. 1A being an electrical diagram and FIG. 1B being a schematical section view of the elementary memory point.
FIG. 1A shows a transistor T of a floating gate memory point. This transistor comprises a floating gate 1 and a control gate 2, together with two semiconductive regions of a first conductivity type (source 3 and drain 4) separated by a channel region having an opposite conductivity type covered by the floating gate 1 and the control gate 2.
The control gate 2 is connected with a word line LM. The drain 4 is connected with a bit line LB.
For writing such a memory point, the floating gate 1 is charged by injection of hot carriers, by applying to the control gate 2, while a current flows between the source 3 and the drain 4, a sufficiently high potential for having the charge carriers (electrons) trapped into the floating gate. This writing operation causes an increase of the conduction threshold of the transistor which, once written (or programmed), will let current flow only for potential values on its control gate higher than when no programmation has been made.
For reading the information contained in a memory point, a voltage higher than the conduction threshold voltage at the non-programmed state and lower than the conduction threshold voltage at the programmed state is applied to the control gate of the transistor of this memory point. If the transistor lets a current flow when a suitable potential difference is applied between the source and the drain, the memory point is at the non-programmed state. If the transistor does not let a current flow, the memory point is at the programmed state.
The voltage applied to the control gate when the memory point is programmed (programmation potential Vpp) is for example equal to 15 volts. The drain potential Vcc is then for example 10 volts and the source potential Vss is for example zero volt (or the ground).
The voltage applied to the control gate during the reading of the memory point is for example 5 volts. The drain potential Vcc is then for example 1.5 volts, and the source potential is then for example zero volt or the ground.
Referring to FIG. 1B that shows a section view of a memory point designed on a silicon wafer, one can see the floating gate 1 and the control gate 2 of the transistor. The source 3 and the drain 4 are two semiconductive regions of a first conductivity type, for example N.sup.+, separated by a channel region 7 of the opposite conductivity type, for example p.sup.-.
The floating gate 1 of the transistor is made of a first polysilicon level (poly 1). The floating gate is separated from the substrate by a silicon dioxide layer 5, also called gate oxide layer.
Above the floating gate 1, is a silicon dioxide layer 6. The layer 6 is arranged between the floating gate 1 and the control gate 2, the latter being made of a second polysilicon level (poly 2). The silicon dioxide layer 6 is also called interpoly oxide layer.
In the memory, the control gate 2 of the transistor is connected to a word line LM. The source 3 is connected to the ground and the drain 4 to a bit line LB.
With a conventional memory architecture and the associated programmation mode, the drain of a transistor has to be electrically isolated by thick silicon oxide with respect to the drain of the adjacent transistors of the same word line. If such an isolation is not carried out, it is not possible to program a specific memory point without programming or deprogramming the other ones at the same time.
However, the thick oxide which isolates two adjacent points takes a large surface, mainly when it results from a localized oxidation process (locos).
It has been suggested to replace the localized oxidation by oxide-filled grooves for reducing the total size of the cell, but this technology is not easy to implement industrially.
French patent application 86/12 940, which corresponds with U.S. Pat. No. 4,887,238, has suggested, for reducing the total size of the memory points and therefore increasing the storage capacity of the memory, to use structures wherein the thick oxide layers and the multiple contacts towards the drains or sources are canceled. Those structures are called checker board structures.
FIG. 2 is a top view of nine adjacent memory points in such a checker board structure.
Tij designates the various floating gate transistors making the memory point array, i being a row index and j a column index.
Thus, transistors T11-T13 constitute the first row, transistors T21-T23 the second row, and transistors T31-T33 the third row. Similarly, transistors T11-T31 constitute the first column, transistors T12-T32 the second column and transistors T13-T33 the third column.
The transistor control gates of a same row are interconnected with a same word line, LM1-LM3 for rows 1-3, respectively.
The word lines are conductors (in practice polysilicon) extending through a horizontal direction (row direction).
Each transistor shares with the two adjacent transistors of the same row a diffused region of the first conductivity type which extends according to a column in order to form a bit line, designated by LB1, LB2, LB3 and LB4 for columns 1-4, respectively, and by LBj in a general way. Those lines LBj therefore correspond, at the position of the transistors, either to the source or to the drain.
FIG. 3 shows a section view along line YY' of FIG. 2.
The components are arranged on a substrate 10. The floating gates 11 of the transistors are made by a first polysilicon level (poly 1) and are arranged between two bit lines. The transistor control gates 12 are formed by the portions of the word line LM2 arranged at the position of the transistors. The word lines, and therefore the transistor control gates, are made by a second polysilicon level (poly 2).
A gate oxide layer 13 is arranged under the transistor floating gate.
An oxide layer 14 is arranged between the transistor floating gates. Conventionally, a planarization process is used for having the upper surfaces of this layer 14 and the upper surfaces of the polysilicon level at the same level. This layer 14 is for example made of tetraethyl ortho silicate or TEOS.
An interpoly oxide layer 15 covers the floating gates 11 and the oxide layers 14.
The programmation mode of such an architecture is specific. It is disclosed in the above mentioned French patent application. This is due to the fact that each memory point shares with each of the two adjacent memory points of the same row a region that can be either a source region or a drain region.
Thus, the programmation of a memory point has to take into account the adjacent memory points. This renders the addressing system very complex.
FIG. 4 is a diagram of the capacitors existing at the position of a transistor, for example transistor T22.
If a voltage V.sub.M is applied to the word line LM2, one obtains the voltage V.sub.F on the floating gate 11 by calculating the coupling factor .gamma. which associates those two voltages according to the relation: EQU V.sub.F =.gamma.V.sub.M
and which is determined by the ratio between the capacitor at the level of the interpoly oxide layer and the sum of all the capacitors.
FIG. 4 shows a capacitor C.sub.OI at the level of the interpoly oxide layer 15 between the word line LM2 and the floating gate 11. There is also a capacitor C.sub.OG at the level of the gate oxide layer 13 between the floating gate 11 and the substrate 10.
The coupling factor .gamma. is defined by: EQU .gamma.=C.sub.OI /(C.sub.OI +C.sub.OG)
A value representative of the coupling factor can be calculated by using the usual values for the size of the elements:
length of the floating gate along the row direction: 0.5 micrometer; PA1 thickness of the interpoly oxide layer: 20 nm; PA1 thickness of the gate oxide layer: 20 nm.
The value of the coupling factor is then equal to the ratio between the quantities 0.5/20 and 0.5/20+0.5/20, that is only 0.5.